/*====激励块: test_Ripplecounter. v ====*/
module test_Ripplecounter();
reg CLR_, CP;
wire [3:0]Q;
Ripplecounter i1 (. CLR_n(CLR_),. CP(CP), . Q(Q));
initial begin //清零信号
CLR_=1'b0;
CLR_=#20 1'b1;
#400 $stop;
end
always begin //时钟信号
CP=1'b0;
CP=#10 1'b1;
#10;
end
endmodule

